The trend in integrated circuits (IC) is to form smaller chips that perform sophisticated functions with high speed. This leads to improvements in computer, communication, and consumer electronics equipment. The devices in the ICs are shrunk down to the deep submicron range in ultra large scale integration (ULSI) technology. Accordingly, the number of devices on a single chip has been increased from a thousand to nearly a billion.
One of the most difficult challenges in fabricating ever shrinking devices is to accurately control the size of various features in the devices. Further, this must be done in a cost effective manner. Accurately controlling feature size is critical in the manufacture of submicron size devices. A dimensional deviation of one hundred angstroms, which may be tolerable in early semiconductor fabrication processes, can cause serious failure in submicron IC's.
The lithography and etching processes are some of the most important processes in defining individual functional regions and determining the feature size of devices. I-line and deep-ultraviolet technology has been used for years for high definition lithography. RIE (reactive ion etching) and MERIE (magnetically enhanced reactive ion etching) are also widely used for achieving better anisotropy.
However, most etching processes have dimensional deviation from the ideal dimension defined on the mask pattern. An after-etched layer for most metal layers has been observed to have a larger dimension than a pattern defined on the covering mask. The problem is typically referred to as the CD (critical dimension) gain of metal etching.
The metal layers are of great importance in forming contacts and interconnections. In a metallization process, a metal layer is formed over a semiconductor. A photoresist layer is formed and patterned to define the pattern of the connective paths. The metal layer is then etched by the pattern defined on the photoresist layer to form the designed connection network. A dielectric layer is then deposited to insulate between individual paths and also between subsequent layers.
However, the problem of the undesired CD gain on the conductors increases the difficulty in depositing dielectric between the conductors. The reliability of the circuit is reduced and the possibility of residue leakage is increased.
There have been some prior art approaches for achieving metal etching with zero bias of the patterned dimension. Techniques such as side-etching or over-etching have been proposed. However, each of these techniques has drawbacks such as lower photoresist selectivity, over-etching from the sides, and residues.
What is needed is a method for solving the CD gain problem in metal etching to provide an etching process with precise dimension control.